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MCH2022 badge pinouts

    Connectors

    SAO (Shitty AddOn)

    Addon connector following the SHITTY ADD-ON V1.69BIS standard.

    PinDescriptionDirectionConnection
    1VCCPower output3.3v supply voltage output
    2GNDPower outputGround reference
    3SDAData IOI2C bus data
    4SCLData outputI2C bus clock
    5GPIO1Data IOUser configurable IO, connected to RP2040 GPIO18
    6GPIO2Data IOUser configurable IO, connected to RP2040 GPIO19

    PMOD (peripheral module interface)

    PMOD

    The PMOD connector is wired up to the iCE40 FPGA. Note that while the connector is physically located on the backside of the badge, it has been wired up such that the PMOD’s top side must be pointed in the same direction as the badge’s top.

    PMOD pinICE40 pinNote
    147IOB_2a (paired with PMOD pin 7 IOB_3b_G6)
    248IOB_4a (paired with PMOD pin 8 IOB_5b)
    34IOB_8a (paired with PMOD pin 9 IOB_9b)
    42IOB_6a
    744IOB_3b_G6 (paired with PMOD pin 1 IOB_2a)
    845IOB_5b (paired with PMOD pin 2 IOB_4a)
    93IOB_9b (paired with PMOD pin 3 IOB_8a)
    1046IOB_0a

    Chips

    ESP32

    ESP32 GPIODirectionFunctionNote
    0BothI2S master clock output / UART download select inputDrives I2S DAC / driven by RP2040 through resistor
    1OutputUART TXConnected to RP2040
    2BothSD card data 0SD card slot
    3InputUART RXConnected to RP2040
    4OutputI2S bit clock
    5OutputLED dataConnected to the SK6805 LEDs in the kite
    12OutputI2S LR channel select
    13OutputI2S data
    14OutputSD clockSD card slot
    15OutputSD commandSD card slot
    18OutputSPI clockConnected to LCD and FPGA
    19OutputSD card and kite LED power controlSet high to enable power to LEDs and SD card
    21OutputI2C clockConnected to RP2040, BNO055, BME680, Qwiic connector and SAO addon connector
    22BothI2C dataConnected to RP2040, BNO055, BME680, Qwiic connector and SAO addon connector
    23OutputSPI MOSIData from ESP32 to LCD / FPGA
    25BothLCD resetSet to output low to reset LCD, leave floating normally
    26OutputLCD modeLow: LCD in SPI mode, high: LCD in parallel mode
    27OutputSPI chip select for ICE40Low: select ICE40, high: deselect ICE40
    32BothSPI chip select for LCDLow: select LCD, high: deselect LCD. Note: output in LCD SPI mode, input in LCD parallel mode
    33BothLCD DC (data or command) selectionNote: output in LCD SPI mode, input in LCD parallel mode
    34InputInterrupt from RP2040
    35InputSPI MISOConnected to ICE40
    36 (SENSOR_VP)InputInterrupt from position sensor (BNO055)
    39 (SENSOR_VN)InputInterrupt from ICE40 FPGA

    RP2040

    RP2040 GPIODirectionPullFunctionDescription
    0OutputUART0 TXESP32 UART
    1InputUART0 RXESP32 UART
    2BothI2C1 SDAI2C bus data (RP2040 is in slave mode)
    3InputI2C1 SCLI2C bus clock
    4InputUpGPIOButton: MENU
    5InputUpGPIOButton: HOME
    6InputUpGPIOButton: ACCEPT
    7InputUpGPIOButton: Joystick A
    8InputUpGPIOButton: Joystick B
    9InputUpGPIOButton: Joystick C
    10InputUpGPIOButton: Joystick D
    11InputUpGPIOButton: Joystick E
    12BothGPIOESP32 bootloader mode¹
    13OutputGPIOESP32 enable
    14BothGPIOESP32 interrupt¹
    15OutputPWMLCD backlight brightness
    16BothGPIOAvailable next to prototyping area
    17BothGPIOAvailable next to prototyping area
    18BothGPIOSAO GPIO1
    19BothGPIOSAO GPIO2
    20InputGPIOFPGA done
    21OutputGPIOFPGA reset
    22InputUpGPIOButton: START
    23InputGPIOLiPo charger state
    24OutputUART1 TXFPGA UART
    25InputUART1 RXFPGA UART
    26InputUpGPIOButton: BACK
    27OutputGPIOInfrared LED
    28InputADCVoltage measurement: USB input
    29InputADCVoltage measurement: Battery

    ¹: Set to input normally and force low to activate

    ICE40 FPGA

    ICE40 pinICE40 GPIODirectionDescriptionNotes
    2IOB_6aBothPMOD pin 4
    3IOB_8aBothPMOD pin 3
    4IOB_9bBothPMOD pin 9
    6IOB_13bInputUART RX
    9IOB_16aOutputUART TX
    10IOB_18aOutputInterruptActive-low
    11IOB_20aOutputLCD register select
    12IOB_22bBothRAM SPI D2
    13IOB_24aBothRAM SPI D1
    14IOB_32a_SPI_SOOutputSPI MISO
    15IOB_34b_SPI_SCKInputSPI SCK
    16IOB_35b_SPI_SSInputSPI SS
    17IOB_33b_SPI_SIInputSPI MOSI
    18IOB_31bOutputRAM SPI CS
    19IOB_29bOutputRAM SPI SCK
    20IOB_25b_G3BothRAM SPI D3
    21IOB_23bBothRAM SPI D0
    23IOT_37aOutputLCD write
    25IOT_36bInputLCD frame sync
    26IOT_39aOutputLCD data 0
    27IOT_38aOutputLCD data 1
    28IOT_41aOutputLCD CS
    31IOT_42bOutputLCD data 2
    32IOT_43aOutputLCD data 3
    34IOT_44bOutputLCD data 4
    35IOT_46b_G0Input12MHz clock
    36IOT_48bOutputLCD resetActive-low, drive open-drain
    37IOT_45a_G1OutputLCD data 5
    38IOT_50bOutputLCD data 6
    39RGB0OutputLED
    40RGB1OutputLED
    41RGB2OutputLED
    42IOT_51aOutputLCD data 7
    43IOT_49aInputLCD modeShould be driven by ESP and monitored by FPGA
    44IOB_3b_G6BothPMOD pin 7
    45IOB_5bBothPMOD pin 8
    46IOB_0aBothPMOD pin 10
    47IOB_2aBothPMOD pin 1
    48IOB_4aBothPMOD pin 2